The present invention relates to an overcurrent protection circuit for an inverter device for preventing an electric valve used in an inverter portion of the inverter device from being damaged by an overcurrent in an event of output short-circuit etc.
FIG. 1 is a circuit diagram of an overcurrent protection circuit of an inverter device used in a conventional inverter of general voltage type and an associated peripheral circuit device. In FIG. 1, a reference numeral 1 depicts a d.c. power source, 2--1 a transistor connected in series to a transistor 2--4, an intermedial point U therebetween being connected to a load 5 and opposite ends of the series connection being connected across the d.c. power source 1, 2--3 a transistor connected in series with a transistor 2--6, an intermedial point V being connected to the load 5 and opposite ends of the series connection being connected across the d.c. power source 1, 2--5 a transistor connected in series with a transistor 2--2, an intermedial point W therebetween being connected to the load 5 and opposite ends of the series connection being connected across the d.c power source 1, 3--1 a diode connected in parallel to the transistor 2--1 such that its conducting direction is opposite to that of the transistor 2--1, 3--2 a diode connected in parallel to the transistor 2--2 in the opposite direction similarly to the diode 3--1, 3--3 a diode connected similarly to the transistor 2--3, 3--4 a diode connected similarly to the transistor 2--4, 3--5 a diode connected similarly to the transistor 2--5, 3--6 a diode connected similarly to the transistor 2--6, 4--1 a current detector inserted between the intermedial point U and the load 5, 4--2 a current detector connected between the intermedial point V and the load 5, 4--3 a current detector connected between the intermedial point W and the load 5, 8 a major priority circuit responsive to outputs of the current detectors 4--1, 4--2 and 4--3 for outputting the largest one of the detector outputs by a comparison of absolute values of them, 9 an overcurrent judging circuit for judging an overcurrent according to an output of the major priority circuit 8, 10 a cut-off signal corresponding to the output of the overcurrent judging circuit 9, 7 a cut-off circuit responsive to an output of a short-circuit preventing circuit 11 and the cut-off signal 10 for outputting a signal to be supplied to bases of the transistor 2--1, 2--2, 2--3, 2--4, 2--5 and 2--6, and 6 a base signal generator, an output of which is an input of the short-circuit preventing circuit 11.
In operation, when an output frequency of the inverter is set by a frequency setting means which is not shown and the output frequency is supplied to the base signal generator 6 as a frequency instruction signal, the base signal generator 6 produces control signals to be supplied to respective transistor of the so-called 180 degree conduction type shown in FIG. 2. Since there is a transistor switching delay, upper and lower transistors of each arm, e.g., the transistors 2--1 and 2--4, 2--3 and 2--6 or 2--5 and 2--2, may be turned on simultaneously. In order to prevent such short-circuit condition from occurring, a dead time td is provided in base signals, i.e., ignition signals, of the upper and lower transistors by passing the output of the base signal generator 6 through the short-circuit preventing circuit 11. FIG. 3 is a circuit diagram of one of six circuit portions constituting the short-circuit preventing circuit 11. Although a detailed description of the short-circuit preventing circuit operation is omitted because it is a mere delay timer, it receives the transistor control signals such as shown in FIG. 2 from the base signal generator 6, delays them by a time determined by a time constant of a resistor R and a capacitor C to delay leading edges by the dead time td and supplies them as transistor base signals having waveforms such as shown in FIG. 4 to the cut off circuit 7. Incidentally, capitals D and B in FIG. 3 depict a diode and a buffer, respectively. When the cut-off circuit 7 has no cut-off signal 10, it operates to supply the transistor base signals from the short-circuit preventing circuit 11 to the respective transistors 2--1 to 2--6 upon which these transistors perform switching operations to supply a.c. power to the load 5. In this case, the diodes 3--1 to 3--6 act as circulating diodes for processing reactive energy of the load 5.
As to an operation of the overcurrent protection circuit, the current detectors 4--1, 4--2 and 4--3 detect currents in U, V and W phases, respectively, convert them into voltage signals and supplies them to the major priority circuit 8 which compares absolute values of the voltage signals with each other and provides a voltage signal having the maximum value as its output. This operation is shown in FIG. 5. The overcurrent judging circuit 9 responds to the output of the major priority circuit and supplies the cut-off signal 10 to the cut-off circuit 7 when the load is increased for some reason and the current is increased thereby. The cut-off circuit 7 responds to the cut-off signals 10 to cut-off the base signals to the transistors 2--1 to 2--6 to thereby prevent the power supply to the load 5. Thus, all of the transistors are protected against damage due to overcurrent.
Among operations of the overcurrent protection circuit, a protection of output short-circuit which provides the stress to the transistors will be described. The term "output short circuit" used here means a state where at least two of the three phases U, V and W are short-circuited simultaneously. Assuming that all of the three phases U, V and W are short-circuited simultaneously, ignition signals to be supplied to the respective transistor 2--1 to 2--6 can be classified into six modes as shown in Table 1 below where the dead time period td and the switching times of the transistor are neglected.
TABLE 1 ______________________________________ upper transistor lower transistor phase U V W U V W transistor 2-1 2-3 2-5 2-4 2-6 2-2 ______________________________________ mode 1 0 0 1 1 1 0 mode 2 0 1 0 1 0 1 mode 3 0 1 1 1 0 0 mode 4 1 0 0 0 1 1 mode 5 1 0 1 0 1 0 mode 6 1 1 0 0 0 1 ______________________________________
In Table 1, "1" signifies an on state of a transistor and "0" signifies an off state of a transistor. From Table 1, it is clear that the transistors are in the following two conditions.
1. two upper transistors are on. (two phases) one lower transistor is on. (one phase) PA1 2. one upper transistor is on. (one phase) two lower transistors are on. (two phases)
Since the above two conditions are relative to each other, mode 6 of the condition 1, i.e, the output phases U, V and W are short-circuited when the transistors 2--1, 2--3 and 2--2 are in on state will be considered as a typical example.
This condition is shown in FIG. 6, and collector currents and collector-emitter voltages of the respective transistors when short-circuited are shown in FIG. 7. In FIG. 7, when a short-circuit occurs at a time t1, collector currents of the respective transistors increase abruptly due to reduction of output impedances thereof. The collector current i(2--2) of the transistor 2--2 is increased up to a value determined by the base current and the specific current amplification factor hFE thereof and clamped thereat. On the other hand, when it is assumed that electric characteristics of the respective transistors are substantially the same, currents flowing through the respective transistors 2--1 and 2--3 become as follows according to Kirchhoff's law. EQU i(2--1)=i(2--3)=1/2i(2--2)
Therefore and since collector current-collector emitter voltage characteristics ic-VcE are non-linear, the transistor 2--2 whose collector-emitter current is the largest owes substantial portion of the voltage while the transistors 2--1 and 2--3 owe small portions thereof as shown in FIG. 7. In other words, the transistor 2--2 is operating in a more active region than those of the transistors 2--1 and 2--3 and, therefore, it is operating under a severe stress condition.
As shown, the current i(2--2), i.e., W phase current, exceeds an overcurrent judging level at the time t2. However, the cut-off operation is started at a time t3 due to response delays of the current detector 4--3, the major priority circuit 8, the overcurrent judging circuit 9 and the cut-off circuit 7 etc., a response delay of base drive circuits which are not shown and response delay of transistors due to storage times thereof etc. Therefore, the transistors to be used should not be damaged even if they are subjected to such currents and voltages for such responsive delay times during short-circuit conditions.
At the time instance t3, the current cut-off operation is started. Since the transistor 2--2 is in the deepest active region as mentioned previously, its storage time is the shortest among others and thus the cut-off operation is started at the highest speed. Therefore, collector currents i(2--1) and i(2--3) of the transistor 2--1 and 2--3 are reduced nominally due to the cut-off operation for the transistor 2--2 at the time t3. The collector current of the transistor 2--2 is then reduced to 0 during a falling time from the time t3 to a time t4 at a current damping rate di/dt and the cut-off is completed at which a spike voltage vP=L di/dt, where L is a wiring inductance, appears in the collector-emitter voltage vCE(2--2) of the transistor 2--2 causing the latter to be severely stressed. In order to restrict this within a reverse bias safety operation area (RBSOA) thereof, snubber circuit is used or transistors having large RBSOA are selected.
As mentioned hereinbefore, the transistor which is turned on by itself is subjected to the heaviest stress during the short-circuit condition.